1. Field of the Invention
The present invention generally relates to a nonvolatile ferroelectric memory device, and more specifically, to a nonvolatile ferroelectric memory device which changes reference voltages and timing logically to directly perform a test on all cells of a chip by using a programmable register.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FRAM’) has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.
The FRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
The technical contents on the above FRAM are disclosed in the Korean Patent Application No. 1999-14400 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FRAM are not described herein.
In the initial development stage of the FeRAM, it is necessary to extract cell data for characteristic evaluation of cell arrays.
However, in a conventional cell array, it is impossible to perform a self-test on characteristics of cells on a chip under development. As a result, the characteristics of cells are indirectly tested with an additional test chip.
Also, an additional test mode setting method is required to perform a test on characteristics of a chip in various regions of the conventional FeRAM. In other words, it is necessary to evaluate cell characteristics by externally regulating levels of sensing reference voltages manually to perform a test only on characteristics of cell arrays. Additionally, for quantitative analysis of characteristics of cell arrays, the levels of the sensing reference voltages are to be set as appropriate levels.
In order to set appropriate levels of the sensing reference voltages in the conventional FeRAM, after metal lines are formed with an additional mask, characteristics of each chip are evaluated. Then, a chip is completed by changing a corresponding layer mask with feedback of the evaluation results on the characteristics.
However, additional masks and additional wafer processes are required to set a test mode, which results in damage to cost and time.